1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to non-volatile memories having a split gate.
2. Related Art
Non-volatile memories (NVMs) have many important uses in combination with other circuitry, especially when power may not always be applied. This can be for power loss or power savings applications. Primarily, NVMs have been floating gate devices, but floating gates have limitations, especially as geometries have gotten smaller. If there is any leakage path, regardless of how localized, to the floating gate, the charge can be completely removed from the floating gate. Thus, nanocrystals and nitride as the storage layer have become of more interest because one leakage path does not discharge the entire storage layer. One of the structures that has been shown to have much promise for programming efficiency is a split gate memory cell using source side injection in which both a control gate and a select gate influence the channel but only the control gate ever has the higher voltage needed for programming and erasing.
Known split-gate memory cell devices use two gates. A first gate is a control gate to control the program and erase operations. A second gate is a select gate to select when the memory bit is to be programmed. Such known split-gate memory cells are therefore bigger than single gate memory devices. Therefore, it is difficult to reduce dimensions of the structures that are used to implement known split-gate memory cells to take advantage of improvements in processing technology. Thus, it is desirable for a split gate cell, as well as an improved method of making such a split gate cell, in which one or more of the desirable improvements are achieved.